答案:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CASESYYI IS PORT( D0,D1,D2,D3: IN STD_LOGIC_VECTOR (3 DOWNTO 0); A: IN STD_LOGIC_VECTOR (1 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END;ARCHITECTURE X OF CASESYYI IS BEGIN PROCESS(D0,D1,D2,D3) BEGIN CASE A IS WHEN "00"=>Y<=D0; WHEN "01"=>Y<=D1; WHEN "10"=>Y<=D2; WHEN "11"=>Y<=D3; END CASE;END PROCESS;END;